Professeur
Faculty of Engeneering (STI) – EPFL
Département ou laboratoire: Embedded Systems Laboratory (ESL) [site web]
david.atienza@epfl.ch
Tél. +41 21 693 11 31
Langues d’enseignement
Français, Anglais
Thèmes de prédilection
Embedded systems design and optimization (hardware and software), ultra-low-power wearable health systems, multi-processor smartphones design.
Compétences élargies
Prof. David Atienza is a faculty member of the Institute of Electrical Engineering at EPFL, and focuses on the definition of reliability-aware design, optimization methodologies and system-level exploration tools for high-performance embedded systems and nano-scale multi-processor system-on-chip (MPSoC) architectures.
Regarding teaching objectives, Prof. David Atienza teaches undergraduate and graduate education programs in embedded systems design and Multi-Processor System-on-Chip architectures (MPSoC) in latest technology nodes, especially with a practical industrial application and professional design perspective.
All the teaching activities of Prof. David Atienza are performed in ELECTRICAL AND ELECTRONICS ENGINEERING in the Section of Electrical Engineering (SEL) at EPFL, specifically at the Bachelor Level, ESL teaches the courses of « Circuits and Systems I » and « Microprogrammed Embedded Systems »
Also, Prof. David Atienza is part of the Master of Science in Electrical engineering of SEL at EPFL, where he and other senior members of ESL teach the Advanced Qt Programming Course for Nokia Smartphones, in cooperation with the Nokia Research Center at the Parc Scientifique of EPFL and the Nokia Forum from the Advanced Educational Division of Nokia in Finland.
Thèmes de recherche spécifique
The main research lines of Prof. David Atienza include, but are not restricted to, the following topics:
* Thermal and reliability exploration frameworks and management approaches for MPSoCs and embedded systems, both at microarchitectural and system level.
* Exploration of synergies between hardware and software components to exploit design trade-offs (area, performance, power) in SoC architectures.
* New techniques for memory hierarchy optimization and the design of dynamic memory management mechanisms in multimedia SoC platforms.
* System-level design and energy management approaches for wireless sensor networks.
* Fault-tolerant circuits and design methodologies for nano-scale electronics made from carbon nanotubes and/or silicon nanowires.